High-bandwidth memory (HBM) is a critical component of AI chips that provides the storage and throughput needed to efficiently train and serve large models. Total HBM bandwidth is thus a rough proxy for the world’s total capacity to serve AI models. In 2025, AI chips consumed over 90% of the HBM industry’s output in terms of revenue.
| Quarter | Chip type | Manufacturer | Cumulative memory (PB) | Cumulative bandwidth (EB/s) |
|---|---|---|---|---|
| Q1 2022 | Other Nvidia | Nvidia | 11.8 | 0.30 |
| Q2 2022 | Other Nvidia | Nvidia | 29.9 | 0.76 |
| Q3 2022 | H100 | Nvidia | 0.5 | 0.02 |
| Q3 2022 | Other Nvidia | Nvidia | 47.1 | 1.20 |
| Q4 2022 | H100 | Nvidia | 3.1 | 0.13 |
| Q4 2022 | Other Nvidia | Nvidia | 58.4 | 1.48 |
| Q4 2022 | TPU v5e | 0.3 | 0.01 | |
| Q4 2022 | Other TPUs | 2.3 | 0.09 | |
| Q1 2023 | H100 | Nvidia | 7.6 | 0.32 |
| Q1 2023 | Other Nvidia | Nvidia | 66.1 | 1.68 |
| Q1 2023 | TPU v5e | 0.9 | 0.04 | |
| Q1 2023 | Other TPUs | 6.2 | 0.24 | |
| Q2 2023 | H100 | Nvidia | 19.7 | 0.82 |
| Q2 2023 | Other Nvidia | Nvidia | 75.9 | 1.97 |
| Q2 2023 | TPU v5e | 2.8 | 0.14 | |
| Q2 2023 | Other TPUs | 8.3 | 0.32 | |
| Q3 2023 | H100 | Nvidia | 40.5 | 1.69 |
| Q3 2023 | Other Nvidia | Nvidia | 87.1 | 2.32 |
| Q3 2023 | TPU v5e | 6.8 | 0.35 | |
| Q3 2023 | Other TPUs | 8.6 | 0.33 | |
| Q4 2023 | H100 | Nvidia | 74.2 | 3.11 |
| Q4 2023 | Other Nvidia | Nvidia | 90.6 | 2.44 |
| Q4 2023 | TPU v5e | 13.0 | 0.66 | |
| Q4 2023 | Other TPUs | 10.0 | 0.37 | |
| Q1 2024 | H100 | Nvidia | 118.3 | 4.95 |
| Q1 2024 | Other Nvidia | Nvidia | 104.0 | 3.00 |
| Q1 2024 | TPU v5e | 19.6 | 1.01 | |
| Q1 2024 | Other TPUs | 17.9 | 0.60 | |
| Q1 2024 | MI300X | AMD | 6.6 | 0.18 |
| Q1 2024 | Other AMD | AMD | 4.3 | 0.12 |
| Q1 2024 | Trainium2 | Amazon | 1.4 | 0.04 |
| Q1 2024 | Trainium1 | Amazon | 3.5 | 0.09 |
| Q1 2024 | Ascend 910C | Huawei | 1.6 | 0.04 |
| Q1 2024 | Ascend 910B | Huawei | 3.2 | 0.13 |
| Q2 2024 | H200 | Nvidia | 4.2 | 0.14 |
| Q2 2024 | H100 | Nvidia | 167.8 | 7.03 |
| Q2 2024 | Other Nvidia | Nvidia | 125.5 | 3.89 |
| Q2 2024 | TPU v5e | 25.6 | 1.31 | |
| Q2 2024 | Other TPUs | 31.7 | 1.00 | |
| Q2 2024 | MI300X | AMD | 22.1 | 0.61 |
| Q2 2024 | Other AMD | AMD | 6.5 | 0.20 |
| Q2 2024 | Trainium2 | Amazon | 4.3 | 0.13 |
| Q2 2024 | Trainium1 | Amazon | 7.0 | 0.18 |
| Q2 2024 | Ascend 910C | Huawei | 3.2 | 0.08 |
| Q2 2024 | Ascend 910B | Huawei | 6.4 | 0.27 |
| Q3 2024 | H200 | Nvidia | 28.4 | 0.97 |
| Q3 2024 | H100 | Nvidia | 217.3 | 9.10 |
| Q3 2024 | Other Nvidia | Nvidia | 151.8 | 4.99 |
| Q3 2024 | TPU v6e | 1.3 | 0.07 | |
| Q3 2024 | TPU v5e | 31.4 | 1.61 | |
| Q3 2024 | Other TPUs | 46.9 | 1.45 | |
| Q3 2024 | MI300X | AMD | 40.2 | 1.11 |
| Q3 2024 | Other AMD | AMD | 12.7 | 0.44 |
| Q3 2024 | Trainium2 | Amazon | 12.0 | 0.36 |
| Q3 2024 | Trainium1 | Amazon | 10.6 | 0.27 |
| Q3 2024 | Ascend 910C | Huawei | 4.8 | 0.12 |
| Q3 2024 | Ascend 910B | Huawei | 9.6 | 0.40 |
| Q4 2024 | B200 | Nvidia | 37.4 | 1.61 |
| Q4 2024 | H200 | Nvidia | 84.8 | 2.89 |
| Q4 2024 | H100 | Nvidia | 239.9 | 10.04 |
| Q4 2024 | Other Nvidia | Nvidia | 183.1 | 6.29 |
| Q4 2024 | TPU v6e | 6.8 | 0.35 | |
| Q4 2024 | TPU v5e | 36.2 | 1.85 | |
| Q4 2024 | Other TPUs | 59.7 | 1.82 | |
| Q4 2024 | MI300X | AMD | 62.4 | 1.72 |
| Q4 2024 | Other AMD | AMD | 19.8 | 0.73 |
| Q4 2024 | Trainium2 | Amazon | 30.2 | 0.91 |
| Q4 2024 | Trainium1 | Amazon | 14.1 | 0.36 |
| Q4 2024 | Ascend 910C | Huawei | 6.4 | 0.16 |
| Q4 2024 | Ascend 910B | Huawei | 12.8 | 0.54 |
| Q1 2025 | B200 | Nvidia | 134.3 | 5.78 |
| Q1 2025 | H200 | Nvidia | 123.4 | 4.20 |
| Q1 2025 | H100 | Nvidia | 244.3 | 10.23 |
| Q1 2025 | Other Nvidia | Nvidia | 217.9 | 7.74 |
| Q1 2025 | TPU v6e | 19.8 | 1.01 | |
| Q1 2025 | TPU v5e | 37.7 | 1.93 | |
| Q1 2025 | Other TPUs | 68.8 | 2.08 | |
| Q1 2025 | MI300X | AMD | 78.7 | 2.17 |
| Q1 2025 | Other AMD | AMD | 28.8 | 0.95 |
| Q1 2025 | Trainium2 | Amazon | 50.4 | 1.52 |
| Q1 2025 | Trainium1 | Amazon | 14.1 | 0.36 |
| Q1 2025 | Ascend 910C | Huawei | 25.6 | 0.64 |
| Q1 2025 | Ascend 910B | Huawei | 14.4 | 0.60 |
| Q2 2025 | B300 | Nvidia | 61.9 | 1.72 |
| Q2 2025 | B200 | Nvidia | 215.4 | 9.27 |
| Q2 2025 | H200 | Nvidia | 152.4 | 5.19 |
| Q2 2025 | H100 | Nvidia | 246.1 | 10.30 |
| Q2 2025 | Other Nvidia | Nvidia | 232.5 | 8.35 |
| Q2 2025 | TPU v6e | 40.9 | 2.10 | |
| Q2 2025 | TPU v5e | 37.7 | 1.93 | |
| Q2 2025 | Other TPUs | 71.8 | 2.17 | |
| Q2 2025 | MI300X | AMD | 87.5 | 2.42 |
| Q2 2025 | Other AMD | AMD | 36.8 | 1.14 |
| Q2 2025 | Trainium2 | Amazon | 74.4 | 2.25 |
| Q2 2025 | Trainium1 | Amazon | 14.1 | 0.36 |
| Q2 2025 | Ascend 910C | Huawei | 44.8 | 1.12 |
| Q2 2025 | Ascend 910B | Huawei | 16.0 | 0.67 |
| Q3 2025 | B300 | Nvidia | 217.5 | 6.05 |
| Q3 2025 | B200 | Nvidia | 280.0 | 12.04 |
| Q3 2025 | H200 | Nvidia | 168.7 | 5.74 |
| Q3 2025 | H100 | Nvidia | 246.9 | 10.34 |
| Q3 2025 | Other Nvidia | Nvidia | 234.2 | 8.42 |
| Q3 2025 | TPU v7 | 9.8 | 0.38 | |
| Q3 2025 | TPU v6e | 64.3 | 3.29 | |
| Q3 2025 | TPU v5e | 37.7 | 1.93 | |
| Q3 2025 | Other TPUs | 71.8 | 2.17 | |
| Q3 2025 | MI300X | AMD | 96.3 | 2.66 |
| Q3 2025 | Other AMD | AMD | 55.9 | 1.65 |
| Q3 2025 | Trainium2 | Amazon | 102.2 | 3.09 |
| Q3 2025 | Trainium1 | Amazon | 14.1 | 0.36 |
| Q3 2025 | Ascend 910C | Huawei | 64.0 | 1.60 |
| Q3 2025 | Ascend 910B | Huawei | 17.6 | 0.74 |
| Q4 2025 | B300 | Nvidia | 431.7 | 12.01 |
| Q4 2025 | B200 | Nvidia | 357.4 | 15.37 |
| Q4 2025 | H200 | Nvidia | 171.8 | 5.85 |
| Q4 2025 | H100 | Nvidia | 247.1 | 10.35 |
| Q4 2025 | Other Nvidia | Nvidia | 234.2 | 8.42 |
| Q4 2025 | TPU v7 | 15.4 | 0.59 | |
| Q4 2025 | TPU v6e | 72.4 | 3.71 | |
| Q4 2025 | TPU v5e | 37.7 | 1.93 | |
| Q4 2025 | Other TPUs | 71.8 | 2.17 | |
| Q4 2025 | MI300X | AMD | 98.5 | 2.72 |
| Q4 2025 | Other AMD | AMD | 86.2 | 2.64 |
| Q4 2025 | Trainium2 | Amazon | 134.4 | 4.06 |
| Q4 2025 | Trainium1 | Amazon | 14.1 | 0.36 |
| Q4 2025 | Ascend 910C | Huawei | 83.2 | 2.08 |
| Q4 2025 | Ascend 910B | Huawei | 19.2 | 0.81 |
As of Q4 2025, the cumulative memory bandwidth of AI chips shipped since 2022 has reached roughly 70 million terabytes per second — around 300,000x more data per second than global internet traffic. We draw figures from financial disclosures from five major chip manufacturers.
Epoch's work is free to use, distribute, and reproduce provided the source and authors are credited under the Creative Commons BY license.
Learn more about this graph
We estimate total HBM bandwidth shipped with AI chips over time by multiplying quarterly shipments by each chip’s known memory bandwidth. When chips come in variants with different bandwidth specifications, we use the most popular variant, or take the geometric mean of all variants if we cannot determine which chip dominated sales.
The main challenge is NVIDIA’s Hopper generation, where financial reporting bundles H100 and H200 shipments even though the two have different memory specifications. We model the transition between the two using a logistic S-curve anchored to six public data points, with uncertainty propagated via Monte Carlo simulation.
Data
Our shipment data comes from the Epoch AI Chip Sales datahub, which provides quarterly estimates with 90% confidence intervals for chips from NVIDIA, AMD, Google, Amazon, and Huawei.
Memory bandwidth per chip comes from manufacturer datasheets, where available. For less well-documented chips (Huawei Ascend 910B/C, AWS Trainium), we use estimates from public reporting. The Chip Sales datahub reports NVIDIA Hopper shipments as a single “H100/H200” category. Because the H200 has 76% more memory than the H100, and Hopper was the best-selling AI accelerator for many quarters, the mix between them meaningfully affects total memory estimates.
Analysis
For each quarter, we sample the number of chips shipped from a log-normal distribution fitted to the datahub’s median confidence interval, then multiply by each chip’s HBM bandwidth. For Hopper chips specifically, we need to estimate what fraction were H200s.
We model the H200 share as a logistic S-curve — a standard shape for production ramp-ups — defined by three quantities: when the crossover occurred (H200s comprised ~50% of Hopper shipments), the rate of the transition from 20% to 80%, and where the share leveled off. Rather than picking fixed values, we sample these from distributions and then reweight each sample by how well it matches six data points:
- Cumulative H200 production ≈ 2 million units. The January 2026 export rule caps China H200 exports at 50% of cumulative US sales. Bloomberg reported that China shipments could reach up to 1 million units, implying a total of ~2M. Reuters reported ~700K H200s in inventory at the start of 2026, consistent with ~1.3M shipped + 700K unsold.
- The share of H200s in Q2 2024 was very small (~5%). Jensen Huang hand delivered the first H200 chip to OpenAI in March 2024, which “entered mass production in late Q2” according to TrendForce reporting. This suggests H200 shipments in Q2 were minimal.
- The share of H200s in Q3 2024 was modest (~25%). TrendForce reported that H200 deliveries began, but that orders were “largely focused on the H100 in the HGX architecture, with the H200’s share remaining limited.”
- H200s comprised the majority of shipped chips by Q4 2024 (~55%). In September 2024, TrendForce reported the H200 was expected to become NVIDIA’s primary shipment driver, replacing the H100. With Blackwell shipments delayed, H200 became the bridge product, and major cloud providers launched H200 instances starting in September 2024.
- By Q1 2025, nearly all Hopper shipments were H200s (~85%). The September 2024 TrendForce report states that “Starting in Q3 […] once customers complete their existing orders, the H100 will naturally phase out, and the H200 will take over as the main product supplied to the market”. We assume that this occurred by Q1 2025.
- ~4 million total non-China Hoppers through October 2025. Jensen Huang disclosed that Hopper chips had sold a total of 4 million units through October 2025, serving as a consistency check on our shipment data.
Samples whose implied H200 shares are more consistent with these data points receive more weight in the final estimates. We report weighted medians and 90% confidence intervals for all quantities.
Limitations
Our data covers the five largest AI chip designers and excludes smaller manufacturers like Groq and Cerebras. We track chips shipped, not chips deployed: there is a lag between shipment and deployment, and some chips may never be deployed, while older chips depreciate.
Several chips are available in multiple variants, which differ somewhat in memory bandwidth. We use the 80GB SXM variants of the A100 and H100, since these are assumed to account for the majority of sales, and the geometric mean of all known variants for the A800 and Ascend 910B. Results are fairly insensitive to these choices; we test sensitivity by bootstrapping over known variants and find a 90% confidence interval of 68 to 75 million TB/s in aggregate bandwidth and 4.0 to 4.5x per year for the growth trend. Memory specifications for Huawei Ascend and AWS Trainium chips are estimates.
